A semiconductor device comprising a high-gain vertical transistor having the characteristics mentioned above is known from a prior-art document, i.e. the Patent EP 0 401 354. This Patent related to a vertical bipolar transistor with a collector region and at least one emitter region, for example of the p-type, adjoining the main surface of a circuit, and an intermediate region, in this case of the n-type. This transistor comprises at its surface an insulating layer in which at least one opening is formed for delimiting the effective electrical contact zone between the emitter region and the metal contact pad for contacting the emitter. The transistor has the characteristic that the emitter region has a constant thickness and a homogeneous doping level such that the diffusion length of the minority carriers injected vertically into this entire region is higher than or equal to the thickness of this emitter region. In addition, the ratio of the surface area of the emitter region to the surface area of the effective electrical contact zone of the emitter is chosen to be higher than or equal to 5, and preferably lies between 20 and 300.
Under these conditions, the known device provides a high current gain .beta. such that:
.beta.=150 if the ratio of the areas is between 5 and 7, PA1 .beta.=1620 (measured), and 1765 (calculated) when the ratio is 146.
This current gain asymptotically approaches a value which is almost reached when the ratio is equal to 300. This is why the above values of between 20 and 300 are preferred for this ratio.
In the realization of this known device, the effective emitter contact zone had a surface area of the order of 16 .mu.m.sup.2, which resulted in an emitter region area of 350 .mu.m.sup.2 for a ratio between the areas of 146. Such an emitter surface area meant that the known vertical transistor could not be included in integrated circuits with a high integration density (LSI or VLSI).
The doping of the emitter layer was of the order of 2.times.10.sup.16 atoms.cm.sup.-1 and the thickness of the emitter region was of the order of 0.8 .mu.m.
The process of manufacturing the vertical transistor disclosed by this Patent EP 0 401 354 comprised the formation of a p-type silicon substrate, of an epitaxial n-type layer, and of an insulation island of SiO.sub.2 for defining the transistor. At the center of the island, a p-type emitter region of 0.6 to 0.8 .mu.m thickness was implanted into the epitaxial n-type layer while an interposed n-type layer was left for forming the base between the implanted p-type emitter region and the p-type substrate which forms the collector of the vertical transistor. Openings were provided in an SiO.sub.2 upper insulating and protecting layer to render possible the manufacture of the various metal contact pads.
Another vertical bipolar transistor, also with a high gain, is known from a second prior-art document, the U.S. Pat. No. 4,007,474. This second document describes a semiconductor device with means for increasing the current gain of a vertical npn bipolar transistor. The emitter region of this transistor is formed by two partial regions: a first partial region of low conductivity (n.sup.-) which has a surface area and a depth which are greater than those of a second partial region of high conductivity (n.sup.+).
Here the thickness of the second n.sup.+ partial region adjoining the surface of the device immediately below the electrical contact zone of the emitter pad is 1 .mu.m, and its doping level with phosphorus in silicon is 10.sup.20 cm.sup.-3.
The thickness of the first n.sup.- partial region considered between the second n.sup.+ partial region and the base layer is between 2 and 5 .mu.m, and its doping level with antimony in silicon is approximately 5.5.times.10.sup.15 cm.sup.-3.
The manufacturing process of the vertical transistor known from this second cited document comprises the formation of an n-type heavily doped substrate for forming the collector, on which an epitaxial layer also of the n-type is realized so as to be used as the collector in conjunction with the substrate, which epitaxial layer has a thickness of 20 .mu.m.
The base layer of 3 .mu.m thickness is realized through p-type diffusion into this epitaxial layer. The n-type emitter regions are formed at the surface with conductivities and thicknesses as given above.
Generally speaking, the transistor disclosed by this second cited document was realized in a technology which was still in use during the period around 1980, and it consisted in the use of layers of the order of 20 .mu.m for realizing the transistors. In this technology, moreover, the emitter contact zone was of approximately the same surface area as the surface area of the emitter itself, and this surface area was preferably as large as possible so as to minimize the resistance.
The total thickness of the first and the second partial emitter regions, considered in vertical direction, is given as smaller than the diffusion length into the weakly doped partial region, and the thickness of the strongly doped region is much smaller than the thickness of the weakly doped region.
In this known device, the weakly doped region is realized by means of an n.sup.- epitaxial layer formed at the surface of a p-doped epitaxial layer which forms the base, all this at the surface of the collector. The strongly doped region is then realized through n.sup.+ diffusion into the epitaxial n.sup.- layer such that it forms a very superficial layer which covers substantially the entire surface of the weakly n.sup.- doped subjacent layer. In this manner the two emitter regions form a stack with a horizontal junction. It is taught that it is important for this horizontal junction between these two regions of strong and weak doping, written L-H, to be at least 4 .mu.m away from the emitter-base junction in vertical direction.
The emitter structure, which is of the LEC (Low Emitter Concentration) type, is indeed of specific shape and dimensions.
Vertical transistors are important for realizing integrated circuits in which the designer wants to include inverting transistors as well as current source transistors. In this case the inverting transistors are mostly realized as lateral transistors, while the current source transistors are vertical transistors.
The current gain factors of vertical transistors are higher (50 to 100) than those of lateral transistors (&lt;50). The first cited prior-art document teaches that the proposed vertical transistor renders it possible to achieve a current gain of the order of 150 to 1800, depending on the surface area ratios employed. The second cited prior-art document squarely states a current gain of the order of 10000 (10.sup.4).
Numerous experiments have been carried out with the object of realizing the said vertical transistor proposed in the second cited document in order to obtain the very advantageous gain which seemed to be possible. This known transistor certainly proved to have a low noise level as described in the cited document.
Nevertheless, it should be taken into account that not only the emitter is weakly doped (5.5.times.10.sup.5 cm.sup.-3) but also the base (10.sup.16 cm.sup.-3). This is the most important phenomenon in this second cited Patent. Experiments have in fact shown that, even if the strongly doped n.sup.++ partial emitter region is not realized in this known device, the prospective gain of 10.000 (10.sup.4) is still obtained. This is due to an error in the physical theory propounded in this patent. The strong gain indeed is not the result of the strongly doped layer but of the fact that the base layer and the main emitter layer are both weakly doped. The injection efficiency is increased by this. In actual fact, the general transistor theory applies to the transistor structure described in this second cited document and not the theory propounded in this document.
The gain increase is accordingly due to a measure (the weak doping of the base) which is not openly stated, but which produces an insurmountable disadvantage: the gain which is held out is in actual fact obtained only when the base and the emitter are simultaneously weakly doped, whether the strongly doped partial emitter region exists or not. This strongly doped region has no part in the results as regards the announced gain because the injection efficiency is not due to surface effects but to the total of the effective impurities in the emitter.
The result is that in most cases this transistor known from the second cited document cannot be used because it has a much too low breakdown voltage owing to the weak doping of the base and emitter regions. To support these conclusions, it is useful to read the publication by H. G. de Graaff and J. W. Slotboom in "Solid State Electronics" no. 19, p. 809, 1976, in which the various aspects of the behavior of transistors with weakly doped emitters (LEC) are described. Generally, in the field of transistors, those skilled in the art must take great care when highly promising results are announced in order to ensure that these results are actually obtained through the described means, and without fatal flaws.
As regards the high-gain transistor known from the first cited prior-art document, on the other hand, this device has the disadvantage that it is very bulky. In the present state of technology it is indeed mainly the object to increase considerably the integration density of active and passive elements on one and the same substrate. This condition is absolutely imperative in the semiconductor industry.
While the device known from the first cited document does not have an attractive gain performance, on the other hand its dimensions render it unsuitable for industrial development of circuits with a very high integration density.
Nevertheless, this known device according to the first prior-art citation (dating from 1988) marks a turning point in the technology of vertical bipolar transistors because its operation is based on surface effects which were completely unknown in the state of the art obtaining until that moment, and corresponds to completely novel theories which are in complete contradiction to the theories on which the previously used state of the art was based, as described in the second cited document (dating from 1977).
To understand the novel theory applied in this Patent EP 0 401 354 (first cited document), those skilled in the art may profitably read the publication with the title "The physics and modeling of heavily doped emitters" by Jesus A. del Alamo and Richard M. Swanson in IEEE Transactions on Electron Devices, vol. ED-31, no. 12, December 1984, pp. 1878-1888. The term "heavily doped emitters" should be understood to cover, at the time of the publication, emitters more strongly doped than so-called LEC transistors, i.e. doped to approximately 10.sup.18 -10.sup.20 cm.sup.-3 for transistors with a thick emitter layer of between 2 and 10 .mu.m. It is evident from this publication that the operation of strongly doped emitters of transistors having thick layers is governed by the transport and the recombination of the minority carriers, but that the mechanisms affecting the lifetime of the minority carriers in the silicon are extremely complex and should be the subject of extensive research. This publication also indicates that in many cases the experimental results are in contradiction to the model results. This results from the fact that, because of the complexity of the phenomena in question, the model formation cannot take into account all parameters. Only intensive research is capable of getting to the heart of the problem relating to the behavior and the recombination time of the minority carriers in the silicon in the emitters of the transistors.
Nevertheless, this publication establishes that this behavior depends on the doping and the thickness of the emitter layer. The device described in the Application EP 0 401 354 (first cited document) realizes a selected number of means which utilize this teaching from the cited IEEE publication for providing the vertical bipolar transistor structure having an improved gain as described. With the appearance of the new theory which has put into practice in this Patent EP 0 401 354, presenting an emitter with an area between 20 and 300 times larger than was usual in conventional devices and an extremely small contact zone area, those skilled in the art were thus obliged seriously to reconsider all which had been the basis of their previous general knowledge, with all the difficulties mentioned in the IEEE publication.
Until the day, therefore, it had been particularly difficult to improve the device described in the Patent 0 401 354 (first cited document); the more so since it was imperative for its industrial use in LSI (Large Scale Integration) circuits with a high integration density or (VLSI) (Very Large Scale Integration) circuits with a very high integration density to reduce its dimensions considerably while preserving the very valuable quality of a strongly increased gain.
It appears now that, far from helping those skilled in the art, new conditions imposed by the evolution of the technologies on the contrary have reinforced the difficulty of resolving this problem. These new conditions result from a recent technological breakthrough which consist in the realization of layers, epitaxial and implanted, with thicknesses which are approximately 2 to 10 times smaller than those obtained in the Patent Application EP 0 401 354 cited above, which leads to thicknesses of the epitaxial layer of the order of 1 .mu.m, in which layer the emitter and base regions are formed with correspondingly small thicknesses. Owing to this evolution, it was found that the gain of the vertical transistors decreased as the thickness of the layers used was reduced. Thus the general insights of those skilled in the art were put into question again, and their experiences acquired in the understanding of the phenomena relating to transistor emitters had to be reconsidered on these new bases, because the old theories on transistors having thick layers were no longer directly applicable.
The device known from the second cited document (U.S. Pat. No. 4,007,474) is considered as not complying with the technological standards and performance requirements of today, and above all as incapable of modification, adaptation or further improvement for achieving those characteristics which are now necessary.